ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870

ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870

This patch enables the workaround for ARM errata 798870 for OMAP5 /
DRA7 which says "If back-to-back speculative cache line fills (fill
A and fill B) are issued from the L1 data cache of a CPU to the
L2 cache, the second request (fill B) is then cancelled, and the
second request would have detected a hazard against a recent write or
eviction (write B) to the same cache line as fill B then the L2 logic
might deadlock."

An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced
here as well.

Signed-off-by: Praveen Rao <[email protected]>
Signed-off-by: Angela Stegmaier <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Tested-by: Matt Porter <[email protected]>
Reviewed-by: Tom Rini <[email protected]>